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Kind code of ref document: Country of ref document: Date of ref document: Year of fee payment: The latch according to the invention is organized into three stages: Each NOR operator 21 of the input stage attack in parallel an OR operator 61 of the second stage and an OR operator 62 of the output stage.
Rat the frequency dividers, for interfacial cage between the signals in GHz and the measurement and control circuits in MHz. The present invention relates to a very fast logic flip-flop, whose structure has been studied in order to simplify the internal organization of the rocker and to improve performance, especially in the very bascuel frequencies between 5 and 10 GHz.
It also relates to the application of the logic flip-flop to a frequency divider by 2, operating the DC to 10 GHz in frequency, this frequency divider being designed in particular in the form of integrated circuit on gallium arsenide. The development of microelectronics microwave, that is to say one that is carried out on new materials type gallium arsenide and other materials derived families III-V and II-VI, required the bascue developing means of control and processing microwave signals.
Indeed, in a microwave system are generally associated means or control and processing elements in the form of integrated circuits working at maximum frequencies of the order of a few hundred MHz. For example, a microwave device on gallium arsenide are often associated circuits on silicon in said ECL technology.
It is therefore necessary to interface the part of the system that works in the microwave generated by circuits on gallium arsenide, and the part of the system that works with circuits made of silicon, and therefore to a division of frequencies to lower GHz to MHz. Without jeopardizing the method of frequency transposition according to which rat given frequency is measured relative to the local frequencies generated basule local oscillators very high stabilities, technical solutions are srt towards the frequency division, s ‘turns out to be very interesting, provided that the divider circuits: In the field of the periodic frequency division, very ret results have been obtained in the band 5 to 15 GHz, using structures using planar Gunn diodes.
The dividers of the best performing aperiodic frequencies work in a wider frequency band, but they require the application of two complementary signals, which is rwt a disadvantage because the complementary signal is easy to generate. The currently known frequency dividers work up to frequencies of 5.
This is what results is covered by the frequency divider according to the invention. The frequency divider according to the invention, basscule is to say also the flip-flop which is the basis bascuke the embodiment of a divider has been designed with a dual purpose. On the one hand, its electric scheme was optimized in order to simplify it, by reducing the number rts stages, thus a reduction of the propagation times through the stages and consequently an increase fst the maximum operating frequency.
Moreover, it is necessary that the selected logical scheme is compatible with the most advanced techniques, especially regarding the dimensioning of the components and their implementation on fast materials of the family of gallium arsenide and compounds III- V.
Indeed, when the operating frequencies of a microelectronic device are measured in GHz, the dimensioning of the components, that is to say for example the gate length of a field effect transistor which takes importance n bqscule is significant since in some cases it is unclear achieve sufficiently fine grids, due to the limits imposed by the masking techniques, although this example is cited only to show the importance of compatibility between the schematic and wiring its realization.
These simplifications are made possible by redundancies between operators, which allowed not to have three floors of operators instead of four between the input and the output of the latch.
The invention will be better understood from the description of the fast flip-flop which is based on the appended figures, which represent: To divide the frequencies in ranges of 5 to 10 GHz, it is clear that one must have recourse to the most advanced techniques and that these frequency dividers are made with high-performance field effect transistors and usually using a technology said logic ret field effect transistors BFL. The divisors of the best performing aperiodic frequencies are obtained by looping a so-called master-slave RS flip-flop shown in Figure 1.
To represent this looped rocking, we keep international symbols and this flip-flop has two basic flip RST.
Both Q and Q outputs of the slave operator are partially looped on the two inputs R and S of the basic master operator Ma. The Q and Q outputs are called complementary. An improvement which allows to double the maximum of a frequency divider in addition to the fact that the master carrier and the slave operator are identical, is to use a clock locking doors, that is to say having a latch RSTT type, wherein T basculle the complementary signal of the input signal T.
Without going into the details of such a scale that is part of the prior art, we see that it consists of four complex operators, two masters complex operators Ma and Ma 2 left of the figure and two complex operators and Esc esc 2 on the right of FIG.
The operators of the output signals are fed back. In this bawcule, the input signals on both inputs E and E must necessarily be complementary. It’s that kind of scale that is used most frequently for the most efficient frequency dividers being made and the architecture used in the prior art, is shown in Figure 3. Actually achieving this feature entirely valid for moderately high frequencies, that is to say until 4 to 5 GHz, is opposed to such operator can operate at higher frequencies.
This is the set of two operators AND basculd the latch which limits the speed of operation of this device.
Logique séquentielle/Mémoires et bascules
These two operators in Figure 4 are surrounded by a dashed rectangle marked 1 are each as regards the, by a field effect transistor with two gates, each gate constituting one of the two inputs of an AND gate. However, firstly the frequency divider designed to work bbascule very baecule frequencies such as 10 GHz, resulting in that the transistors are extremely small dimensions and even smaller grids and thus reach the limits of technology.
But rstt is interesting in some cases to have more than two inputs: By way of example and comparison, the frequency dividers of the prior art currently operate at maximum operating frequencies from 4.
Go beyond these frequencies thus required a change in design and the design of the latch. It is that shown by Figure 5.
Bascule rst pdf
An approximation must be made between the flip-flop of Figure 2 and that of Figure 6. Indeed, while the flip-flop of Figure 2 used two complex masters operators Ma and Ma 2 and two complex operators Esc slaves 1 and Esc 2 include the same configuration master-slave flip-flop of Figure 6, divided over the drawing by two dotted lines that define the master and slave traders.
The master operator Ma is constituted of elementary operators 21, 31 and 61, the master operator Ma 2 consists of elementary operators 41, 51 and The Esc one slave operator complex consists of elementary operators 22, 32 and 6. These operators are looped between them, they receive complementary signals T and T, and deliver output signals Q and Q of quite comparable to the flip-flop of Figure 2.
However, the flip-flop 6 is composed of operators NOR and OR, according to the logic diagram of Figure 5, and this configuration makes it possible to use in the actual integration on a semiconductor wafer, of the transistors to a single grid, as shown in the electrical diagram of Figure 7.
On this wiring diagram, there are two operators NOR, represented by the three transistors framed by a dotted line and marked 8 and 9, and an OR operator consisting of the set of two transistors 10 and The primary interest of this kind structure is that the transistors used in NOR operators for the inputs labeled A, B, C and D are single-gate transistors, that is to say it will be possible to carry out dimensional grids much smaller corresponding to greater frequencies. The second advantage is that the functions OR and NOR are separated, and this advantage will be shown later.
The operating frequency thus passes to 4. However, it can be seen that the rocker of Figure 6 comprises four stages of elementary operators, that is to say a first stage of NOR operators 21,31,41,51, a second stage of operators OR 61, 71, a third stage of NOR operators 22, 32, 42, 52, and a fourth stage of OR operators 62, This means that the transition time through the flip-flop is equal to the sum of the transition time through each of the four floors.
It is possible to improve the total transition time of the latch, that is to say, its operating frequency, so to simplify this flip-flop to reduce the number of stages. In fact, one can consider a number of redundancies that can remove elementary operators in the complemented latch of Figure 6.
The OR operator of the second stage 61 delivers on its output a signal which is simultaneously applied to NOR operators 41 of the first floor and 22 on the third floor: Similarly, the OR operator of the second stage 71 delivers on its output a signal applied simultaneously NOR operators of the first stage 31 and third stage Furthermore, the OR operator 62 of the fourth stage delivers at its output a signal applied in parallel to the NOR operator of the first stage 51 and the NOR operator 42 of the third floor.
Finally the OR operator 72 of the fourth stage simultaneously delivers a signal to the NOR operator of the first stage 21 and the NOR operator 32 of the third floor. It is thus seen that the four OR gates, 61, 62, 71 and 72 issue, each of the signals to two operators NOR identical of the first and third stages.
So there is redundancy between the first and third floor, it is possible to remove the third floor to compact the rocker: To facilitate comparison, Figure 8 and Figure 6, the same reference indices are preserved when they designate the same basic operators. Since elementary operators NOR third floor in Figure 6 all have parallel functions to those of elementary operators of the first floor, the operators of the third floor were removed, which saves on the overall delay of the circuit.
The divider 2 according to the invention therefore appears to be essentially constituted by two complex operators Ma 1 and Ma 2, which control two elementary OR operators 62 and The complex operators Ma and Ma 2 are decided in Figure 8 by two dotted lines and the name of Ma. Ma 2 and is retained by analogy with Figure 6 as these complex operators consist of the same complementary operators.
Similarly, the two output OR operators are those which constitute the fourth stage of the divider by 2 in Figure 6. Meanwhile, the output 12 of the first NOR operator 21 of the first control input of the first OR operator 62 of the third floor, and the output 13 of the second NOR operator 31 of the first stage control input the second OR operator 72 of the third floor. The output 14 of the first OR operator 61 of the second stage is fed back to an input of the third NOR operator 41 of the first stage.
The wiring pattern is symmetric to the second complex operator Ma 2 made up of operators 41, 51, The output 18 of the OR operator 72 of the third stage is fed back to an input of the first NOR operator 21 of the first stage, and the output 19 of the OR operator 62 of the third stage is fed back an input of the fourth NOR operator 51 of the first stage.
Complex operators Ma and Ma 2 are the first and the second stage of the divider by 2 according to the invention. Operators OR outputs 62 and 72 deliver signals Q and Q, further, the frequency is half of the input frequency on additional inputs E and E: Thus, by way of example, the maximum frequency of the frequency divider according to the invention is 6. But by total optimization of the parameters of the circuit, and particularly the dimensioning of the transistors, with 0.
Figure 9 shows the circuit diagram of the latch according to the invention and sets of components which constitute elementary operators are surrounded by a dashed line for ease of identification. The NOR operators 21, 31, 41 and 51 are in the four corners of the figure and constitutes the first stage of the divider by 2. OR operators 61 and 71 are arranged on the vertical diagonal of the figure and constitutes the second stage of the divider by 2.
OR operators 62 and 72 are disposed on the horizontal diagonal of FIG and constitutes the third stage of the divider by 2. RSTT the flip-flop according to the invention was developed for the realization of a frequency divider by 2, characterized by a very wide band of operation since its operation has been checked between the continuous and the X-band that is ie 10 GHz. This circuit is used in the interfaces between the very high frequencies that are measured in GHz and the monitoring or analysis systems operating at lower frequencies that are measured in MHz.
The present invention rocker and frequency divider 2 is specified by the following claims.
Logical flipflop as claimed in Claim 1, characterized in that, for each of the four operators of the input stage 21, 31, 41, 51their output signal is sent in parallel to an OR operator of the second stage 61, 71 and to an OR operator of the third stage 62, Logical flipflop as claimed in Claim 1, characterized in that: A scale according to any one of claims 1 to 4, characterized in that it is made of monolithic circuit on a crystal of semiconductor material, using a single gate transistor technology.
A frequency divider operating in the range 0 to 10 GHz, characterized in that it comprises at least a logic flip-flop according to any one of claims 1 to 5.
Logic latch operating from dc to 10 ghz, and frequency divider comprising this latch. Latch or phase detector circuit for DRAM data storage uses flip flop stage and cascaded NAND gates to give output depending on clock and data state change phase. General purpose divide by two logic circuit – has four similar gates and logic inverter composed of transistor stages.
Linear combination of atomic orbital-molecular orbital treatment of the deep defect level in a semiconductor: Method of combining an analysis filter bank following a synthesis filter bank and structure therefor. Semiconductor device including embedded crystalline back-gate bias planes, related design structure and method of fabrication. Van Der Wel et al. Digital phase-locked loop circuit including a phase delay quantizer and method of use. B1 Designated state s: DE Date of ref document: Lapsed in a contracting state announced via postgrant inform.